Applications and handheld devices play a major role in ensuring comfort in our day- today life. These applications run on handheld electronic gadgets with high-end microprocessor support. Modern CPU designers handle challenges imposed by these applications with cost effective architectural enhancements. This course provides a deeper insight into the design of high-end microprocessors that will support the future applications.
INTENDED AUDIENCE: Anyone in CSE and related fields (like ECE, EEE, IT etc.) with an interest of exploring Computer Architecture PREREQUISITES: A basic understanding of Computer Organisation and Architecture or Microprocessors INDUSTRY SUPPORT: Intel, AMD, IBM, Nvidia etc.
COURSE LAYOUT Week 1: Review of Basic Computer Organization, Performance Evaluation Methods, Introduction to RISC Instruction Pipeline, Instruction Pipeline and Performance. Week 2: Pipeline Hazards and Analysis, Branch Prediction, MIPS Pipeline for Multi-Cycle Operations. Week 3: Compiler Techniques to Explore Instruction Level Parallelism, Dynamic Scheduling with Tomasulo’s Algorithm and Speculative Execution. Week 4: Advanced Pipelining and Superscalar Processors, Exploiting Data Level Parallelism: Vector and GPU Architectures, Architectural Simulation using gem5. Week 5: Introduction to Cache Memory, Block Replacement Techniques and Write Strategy, Design Concepts in Cache Memory. Week 6: Basic and Advanced Optimization Techniques in Cache Memory, Cache Optimization using gem5. Week 7: Introduction to DRAM System, DRAM Controllers and Address Mapping, Secondary Storage Systems, Design Concepts in DRAM and Hard Disk. Week 8: Tiled Chip Multicore Processors(TCMP), Routing Techniques in Network on Chip(NoC), NoC Router Microarchitecture, TCMP and NoC: Design and Analysis, Future Trends in Computer Architecture Research.