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Online Course

CMOS Digital VLSI Design

Indian Institute of Technology Roorkee and NPTEL via Swayam

45

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Overview

This course brings circuit and system level views on design on the same platform. The course starts with basic device understanding and then deals with complex digital circuits keeping in mind the current trend in technology. The course follows a design perspective, starts from basic specifications and ends with system level blocks. Eight Assignments are provided which will add/help in understanding the course in a better manner both at conceptual as well as hands-on level. 

Syllabus

Week 1  :  MOS Transistor Basic-I; L2: MOS Transistor Basic-I; L3: MOS Transistor Basic-II; L4: MOS Parasitic & SPICE Model; L5: CMOS Inverter Basics-I
Week 2  :  CMOS Inverter Basics-II; L2: CMOS Inverter Basics-III; L3: Power Analysis-I; L4: Power Analysis-II; L5: SPICE Simulation-I
Week 3  :  SPICE Simulation-II; L2: Combinational Logic Design-I; L3: Combinational Logic Design-II; L4: Combinational Logic Design-III; L5: Combinational Logic Design-IV
Week 4  :  Combinational Logic Design-V; L2: Combinational Logic Design-VI; L3: Combinational Logic Design-VII; L4: Combinational Logic Design-VIII; L5: Combinational Logic Design-IX
Week 5  :  Combinational Logic Design-X; L2: Logical Efforts-I; L3: Logical Efforts-II; L4: Logical Efforts-III; L5: Sequential Logic Design-I
Week 6  :  Sequential Logic Design-II; L2: Sequential Logic Design-III; L3: Sequential Logic Design-IV; L4: Sequential Logic Design-V; L5: Sequential Logic Design-VI
Week 7 :  Sequential Logic Design-VII; L2: Sequential Logic Design-VIII; L3: Clocking Strategies for Sequential Design-I; L4: Clocking Strategies for Sequential Design-II; L5: Clocking Strategies for Sequential Design-III
Week 8  :  Clocking Strategies for Sequential Design-IV; L2: Sequential Logic Design-IX; L3: Clocking Strategies for Sequential Design-V; L4: Concept of Memory & its Designing-I; L5: Concept of Memory & its Designing-II

Taught by

Prof. Sudeb Dasgupta

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