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Indian Institute of Technology Madras

Mapping Signal Processing Algorithms to Architectures

Indian Institute of Technology Madras and NPTEL via Swayam


Digital Signal Processing typically involves repetitive computations being performed on streams of input data, subject to constraints such as sampling rate or desired throughput. Often such systems need to be implemented under tight constraints on factors such as timing, resources, power or cost. When they are used in embedded systems, it is often worth the effort to design custom architectures that have much better cost tradeoffs than general purpose computing architectures. This course deals with the analysis of such algorithms, and mapping them to architectures that are either custom designed or have specific extensions that make them better suited to certain kinds of operations. Topics covered include fundamental bounds on performance, mapping to dedicated and custom resource shared architectures, and techniques for automating the process of scheduling. Aspects of architectures such as memory access, shared buses, and memory mapped accelerators will be studied. Assignments will cover various aspects of the design process, starting from implementing and testing specifications, to synthesis and scheduling using high level synthesis tools, and analyzing and improving the resulting architectures. INTENDED AUDIENCE: Students interested in hardware (VLSI / FPGA) implementations of DSP systems; also useful for those using custom parallel architectures (GPU) PREREQUISITES: Digital Design fundamentals (UG) - Digital Signal Processing (UG) - Processor architecture (UG)



Week 1: Review: Digital systems, DSP, computer architecture Week 2,3: DSP system models; quality metrics and bounds; number representations Week 4,5,6: Implementation: dedicated hardware; transforms; resource sharing; Scheduling: time and resource bounds; allocation, binding, scheduling,techniques Week 7,8,9: Architectures: programmable systems; FSMs and microprograms; instruction extensions; peripheral accelerators Week 10,11: Memory and communication systems: bus structures; DMA; networks-on-chip Week 12: Specialized architectures: Systolic arrays; CORDIC; GPU

Taught by

Prof.Nitin Chandrachoodan

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