RISC-V Vector CPU Design for High-Performance Computing

Watch a technical seminar where Dr. Filippo Mantovani from the Barcelona Supercomputing Center explores the development of RISC-V-based processors for High Performance Computing (HPC) as part of the European Processor Initiative (EPI). Gain detailed insights into RISC-V architecture, vector supercomputing, and the specific implementation of RISC-V vector extensions (RVV) with large 16-kbit wide vectors. Learn about the methodologies, tools, and libraries available for vectorization while understanding their challenges and limitations. Discover how this innovative approach compares to other vector architectures and its potential impact on the HPC ecosystem. Benefit from Dr. Mantovani's extensive experience in computational physics and high-performance computing, including his work on projects like Janus, QPACE, and Mont-Blanc, as well as his current leadership in FPGA prototyping of RISC-V-based accelerators.