This course covers topics in Computer Organisation and Architectures, such as Von Neumann Architecture and Stored Memory Concept, types of buses (Address, Data and Control), Instruction Format, and explaining the differences between Single Accumulator, General Register, and Register Stack Organisation. Instruction formats, addressing modes, memory hierarchy, cache mapping techniques, and pipelining are discussed. I/O organisation topics, such as priority base interrupt, parallel priority interrupt, and Direct Memory Access (DMA) are studied. Finally comparison between RISC and CISC architectures are made. At the end of this course, the learner will be able to understand the major principles, structures, elements, and concepts in Computer Organisation and Architecture.
Overview
Syllabus
L-1.1: Computer Organization and Architecture Syllabus Discussion for GATE and UGC NTA NET.
L-1.2: Von Neumann's Architecture | Stored Memory Concept in Computer Architecture.
L-1.3:Various General Purpose Registers in Computer Organization and Architecture.
L-1.4:Types of Buses (Address, Data and Control) in Computer Organization and Architecture.
L-1.5: Common bus system using multiplexer | Computer organization and Architecture.
L-1.6: Common Bus system| How basic computer works.
L-1.7: Types of Instructions in General Purpose Computer | Computer Organization and Architecture.
L-1.8: Data Transfer Instructions in Computer Organisation and Architecture.
L-1.9: Arithmetic Instructions(Data Manipulation) in Computer Organisation and Architecture.
L-1.10: Logical Instructions(Data Manipulation) in Computer Organisation and Architecture.
L-1.11: Shift Instructions(Data Manipulation) in Computer Organisation and Architecture.
L-1.12: Program Control Instructions(Types of Control Instructions) | Computer Organization.
L-1.13: What is Instruction Format | Understand Computer Organisation with Simple Story.
L-1.14: Question on Instruction Format | Computer Organization | UGC NTA NET June 2021.
L-1.15: Single Accumulator CPU Organisation | Single Address Instructions in Computer Organisation.
L-1.16: General Register CPU Organisation | Two and Three Address Instructions | COA.
L-1.17: Register Stack Organisation | Zero Address Instructions | COA.
L-1.18:Memory Stack Organisation | Memory stack Vs Register stack | COA.
L-2.1: What is Addressing Mode | Various Types of Addressing Modes | COA.
L-2.2: Implied Addressing Mode | Computer Organisation and Architecture.
L-2.3: Immediate Addressing Mode | Computer Organisation and Architecture.
L-2.4: Register Mode | Addressing Mode | Computer Organisation and Architecture.
L-2.5: Register Indirect Mode | Addressing Modes | Computer Organisation and Architecture.
L-2.6: Auto Increment and Decrement Addressing Modes | Computer Organisation and Architecture.
L-2.7: Direct Addressing Mode || Computer Organisation and Architecture.
L-2.8: Indirect Addressing Mode | Computer Organisation and Architecture.
L-2.9: Relative Addressing Mode || Computer Organisation and Architecture.
L-2.10: Base Register Addressing Mode || Computer Organisation and Architecture.
L-2.11: Indexed Addressing Mode || Computer Organisation and Architecture.
L-2.12: Question on Addressing Modes | Computer Organization | UGC NTA NET 2021.
L-3.1: Memory Hierarchy in Computer Architecture | Access time, Speed, Size, Cost | All Imp Points.
L-3.2: Independent vs Hierarchical Memory Organisation | 2-Level Memory Organisation.
L-3.3: 3-Level Memory Organisation || Computer Organisation and Architecture.
L-3.4: GATE 2004 Question on 3-Level Memory Organisation || Computer Organisation and Architecture.
L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture.
L-3.6: Direct Mapping with Example in Hindi | Cache Mapping | Computer Organisation and Architecture.
L-3.7: GATE 2005 Question on Direct Mapping | Cache Mapping Questions | Computer Organisation.
L-3.8: Fully Associative Mapping with examples in Hindi | Cache Mapping | Computer Organisation.
L-3.9: Advantages and Disadvantages of Direct Mapping | Cache Mapping | Computer Organisation.
L-3.10: Set Associative Mapping with Examples in Hindi | Cache Mapping | Computer Organisation.
L-3.11: Locality of Reference in Cache Memory | Spatial Vs Temporal Locality | Computer Organisation.
L-3.12: Cache Replacement Algorithms in Computer Organisation and Architecture.
L-3.13: LRU (Least Recently Used) Cache Replacement Algorithm | Computer Organisation & Architecture.
L-3.14: Gate 2014 Question on Set Associative Cache Mapping | Computer Organisation and Architecture.
L-3.15: FIFO Cache Replacement Policy with example | Computer Organisation and Architecture.
L-3.16: LRU(least recently used ) Cache Replacement Policy | Computer Organisation and Architecture.
L-4.1: Pipelining with real life example| Need of Pipelining | COA.
L-4.2: Pipelining Introduction and structure | Computer Organisation.
L-4.3: Pipelining Vs Non-Pipelining | Instruction Execution | Speedup, Efficiency, Utilization | COA.
L-4.4: Stage Delay in Pipeline | Previous Year GATE Question | Computer Organisation & Architecture.
L-4.5: Numerical Question on Pipelining | Previous year GATE Question | COA.
L-4.6: What is Hazard in Pipelining | various types of Hazards | computer Architecture.
L-4.7: Structural Hazards in Pipelining | Types of Hazards with Example in Hindi.
L-4.8: Control Hazards in Pipelining | Types of Hazards with Example in Hindi.
L-4.9: What is Read After Write(RAW) Hazards| Data Hazard in Pipelining with Example in Hindi | COA.
L-4.10: Write After Read Hazard with Example|Data Hazards| Computer Organisation and Architecture.
L-4.11: Write After Write Hazard | Data Hazards in Pipelining | Computer Organization &&Architecture.
I/O Interface in Computer Organization.
Daisy Chaining in Priority Interrupt | Priority Based Interrupt in I/O Organization.
Parallel priority interrupt | I/O organization.
Question on Interrupt Handling(I/O organization) | Computer Organization | UGC NTA NET June 2021.
Question on DMA (Direct Memory Access) | Input/Output Organization| COA | UGC NTA NET June 2021.
RISC vs CISC | Computer Organization & Architecture.
Taught by
Gate Smashers
