Overview
This video tutorial guides you through building 256 bytes of random access memory within a digital logic simulation. Follow along as the creator explores the fundamentals of computer memory architecture, starting with basic latches and progressing through decoders, 1-bit memory cells, and both dynamic and static memory concepts. Learn how to scale up from 16 bits to a full 256 bits of memory, and understand the differences between asynchronous and synchronous RAM implementations. The tutorial also covers important concepts like memory caches and equality chips, concluding with practical tests of the memory system. Part of a larger series exploring computer fundamentals, this hands-on demonstration includes access to the simulation software and source code for those who want to experiment themselves.
Syllabus
00:00 Intro and a New Simulation
01:50 A Grid of Latches
03:12 Decoder
04:42 1-Bit Memory Cell
06:42 Rambling about Dynamic and Static Memory
08:46 16 Bits of Memory
11:41 Surprise Inspection
12:16 256 Bits of Memory
14:28 Asynchronous RAM
18:02 A Brief Note Concerning Caches
19:00 Synchronous RAM
22:28 Equality Chip
23:28 The Final Test
24:37 A Trip Down Memory Lane
Taught by
Sebastian Lague