Embedded Systems - Design Verification and Test

Embedded Systems - Design Verification and Test

NPTEL IIT Guwahati via YouTube Direct link

Hardware Architectural Synthesis – 3

10 of 38

10 of 38

Hardware Architectural Synthesis – 3

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Classroom Contents

Embedded Systems - Design Verification and Test

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  1. 1 Embedded Systems - Design Verification and Test [Introduction Video]
  2. 2 Introduction
  3. 3 Modeling Techniques – 1
  4. 4 Modeling Techniques – 2
  5. 5 Hardware/Software Partitioning - 1
  6. 6 Hardware/Software Partitioning - 2
  7. 7 Introduction to Hardware Design
  8. 8 Hardware Architectural Synthesis – 1
  9. 9 Hardware Architectural Synthesis – 2
  10. 10 Hardware Architectural Synthesis – 3
  11. 11 Hardware Architectural Synthesis – 4
  12. 12 Hardware Architectural Synthesis – 5
  13. 13 Hardware Architectural Synthesis – 6
  14. 14 Hardware Architectural Synthesis – 7
  15. 15 System Level Analysis
  16. 16 Uniprocessor Scheduling – 1
  17. 17 Uniprocessor Scheduling – 2
  18. 18 Multiprocessor Scheduling – 1
  19. 19 Multiprocessor Scheduling – 2
  20. 20 Introduction and Basic Operators of Temporal Logic
  21. 21 Syntax and Semantics of CTL
  22. 22 Equivalence between CTL formulas
  23. 23 Model Checking Algorithm
  24. 24 Binary Decision Diagram
  25. 25 Use of OBDDs for State Transition System
  26. 26 Symbolic Model Checking
  27. 27 Introduction to Digital VLSI Testing
  28. 28 Automatic Test Pattern Generation (ATPG)
  29. 29 Scan Chain based Sequential Circuit Testing
  30. 30 Software-Hardware Co-validation Fault Models and High Level Testing for Complex Embedded Systems
  31. 31 Testing for embedded cores
  32. 32 Bus and Memory Testing
  33. 33 Testing for advanced faults in Real time Embedded Systems
  34. 34 BIST for Embedded Systems
  35. 35 Concurrent Testing for Fault tolerant Embedded Systems - 1
  36. 36 Concurrent Testing for Fault tolerant Embedded Systems - 2
  37. 37 Testing for Reprogrammable hardware
  38. 38 Interaction Testing between Hardware and Software

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