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This 18-minute conference talk from USENIX FAST '25 presents an innovative solution for addressing performance bottlenecks in disaggregated storage systems. Explore HiDPU, a hybrid indexing scheme specifically designed for Data Processing Units (DPUs) that tackles the significant CPU computation overhead and high memory consumption during address translation. Learn how researchers from Shandong University, Tianjin University, Huawei Technologies, and The Chinese University of Hong Kong developed a multi-level indexing structure that overcomes DPU limitations including restricted memory resources, constrained computational power, and high DPU-host interaction overhead. Discover their approach of dividing mapping entries into different segment types (accurate, PTHash, and LPTHash) and implementing a layered learned index to enhance memory efficiency. The presentation details a two-phase asynchronous index update strategy that maintains consistency while minimizing performance impact. Experimental results on Huawei's Hi1823 DPU demonstrate impressive achievements: up to 92% memory savings and query performance improvements of up to 6.3 times compared to existing solutions.