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Intel FPGA Technical Training

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Syllabus

Introduction to Parallel Computing with OpenCL™ on FPGAs.
VHDL Basics.
Verilog HDL Basics.
Introduction to High-Level Synthesis (Part 1 of 7).
HLS Interfaces (Part 2 of 7).
HLS Loop Optimizations (Part 3 of 7).
HLS Data Types (Part 4 of 7).
HLS Local Memory Optimizations (Part 5 of 7).
HLS Performance Optimization (Part 6 of 7).
HLS Optimization Example: Matrix Decomposition (Part 7 of 7).
Thermal Management in Intel® Stratix® 10 Devices.
Stratix® 10 HyperFlex™ Architecture Overview.
Platform Designer in the Intel® Quartus® Prime Pro Edition Software.
Advanced System Design Using Platform Designer: Component & System Simulation.
The Quartus Prime Software: Foundation (Pro Edition) (Online Training).
Basics of Programmable Logic: History of Digital Logic Design.
Basics of Programmable Logic: FPGA Architecture.
SignalTap II Logic Analyzer: Triggering Options, Compilation, & Device Programming.
SignalTap II Logic Analyzer: Data Acquisition & Additional Features.
OpenCL™: Single-Threaded vs. Multi-Threaded Kernels.
Creating a System Design with Platform Designer: Getting Started.
Creating a System Design with Platform Designer: Finish the System.
Application Development on the Acceleration Stack for Intel® Xeon® CPU with FPGAs.
DSP Builder Advanced Blockset: Getting Started.
Advanced System Design Using Platform Designer: System Verification with System Console.
The Nios® II Processor: Introduction to Developing Software.
DSP Builder Advanced Blockset: Using Primitives.
Advanced System Design Using Platform Designer: System Optimization.
Memory Optimization for OpenCL™ on Intel® FPGAs.
DSP Builder Advanced Blockset: Interfaces and IP Libraries.
Using Channels and Pipes with OpenCL™ on Intel® FPGAs.
Intel® Hyperflex™ FPGA Architecture Design: Analyzing Critical Chains.
Creating High-Performance Designs for Intel® Stratix® 10 FPGAs.
Intel® Stratix® 10 SoC FPGA Technical Overview.
Introduction to Memory Interfaces IP in Intel® FPGA Devices.
Integrating Memory Interfaces IP in Intel® FPGA Devices.
Verifying Memory Interfaces IP in Intel® FPGA Devices.
On-Chip Debugging of Memory Interfaces IP in Intel® FPGA Devices.
Configuration Schemes for Intel® FPGAs.
Introduction to Configuring Intel® FPGAs.
Fast & Easy I/O System Design with Interface Planner.
Deploying Intel® FPGAs for Deep Learning Inferencing with OpenVINO™ Toolkit.
How to Begin a Simple FPGA Design.
Running OpenCL™ on Intel® FPGAs.
Writing OpenCL™ Programs for Intel® FPGAs.
SEU Mitigation in Intel® FPGA Devices: Fault Injection.
Mitigating Single Event Upsets in Intel® Arria® 10 and Intel Cyclone® 10 GX Devices.
Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer.
Designing with Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX Hard IP for PCI Express*.
Customizing Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX FPGA Hard IP for PCI Express*.
The Nios® II Processor: Hardware Abstraction Layer.
OpenCL™ Development with the Acceleration Stack for Intel® Xeon® CPU with FPGA.
OpenCL™ Coding Optimizations for Intel® Stratix® 10 Devices.
HLS Coding Optimizations for Intel® Stratix® 10 Devices.
Introduction to Intel® FPGAs for Software Developers.
Profiling Intel® SoC FPGAs with Arm* Streamline.
Remote System Upgrade in Intel® MAX® 10 Devices.
Command Line Scripting.
The Nios® II Processor: Booting.
Introduction to the Low Latency 10Gb Ethernet MAC Intel® FPGA IP Core.
Timing Closure Using Timing Analyzer Custom Reporting.
Introduction to the Acceleration Stack for Intel® Xeon® CPU with FPGA.
Creating Reusable Design Blocks: Introduction to IP Reuse with the Intel® Quartus® Prime Software.
Creating Reusable Design Blocks: IP Integration with the Intel® Quartus® Prime Software.
Advanced System Design Using Platform Designer: Utilizing Hierarchy.
Introduction to the 10Gb Ethernet PHY Intel® FPGA IP Cores.
Creating Reusable Design Blocks: IP Design & Implementation with the Intel® Quartus® Prime Software.
Migrating to the Intel® Quartus® Prime Pro Edition Software.
Best Design Practices for Timing Closure.
Using the Intel® Quartus® Prime Standard Edition Software: An Introduction.
Intel® Quartus® Prime Software Tcl Scripting.
Read Me First!.
High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: Introduction, Architecture.
High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: HBMC Features.
High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: Implementation.
Introduction to Cloud Computing.
Custom Component Development Using Avalon® and Arm* AMBA* AXI Interfaces.
Using the Generic Serial Flash Interface.
Building an RTL Module for the Intel® FPGA SDK for OpenCL™.
Transceiver Toolkit for Intel® Stratix® 10 Devices.
Building RTL Workloads for the Acceleration Stack for Intel® Xeon® CPU with FPGAs.
Debugging JTAG Chain Integrity.
Using Design Space Explorer.
Power Analysis.
Incremental Optimization with the Intel Quartus Prime Pro Edition Software.
Partial Reconfiguration for Intel FPGA Devices: Introduction & Project Assignments.
Partial Reconfiguration for Intel FPGA Devices: Design Guidelines & Host Requirements.
Partial Reconfiguration for Intel FPGA Devices: PR Host IP & Implementations.
Partial Reconfiguration for Intel FPGA Devices: Output Files & Demonstration.
Using the Intel Quartus Prime Pro Edition Synthesis Engine.
SignalTap II Logic Analyzer: Introduction & Getting Started.
Intel® Stratix® 10 FPGA Optimization: Loop Analysis and Solutions.
Programmers’ Introduction to the Intel® FPGA Deep Learning Acceleration Suite.
Using Intel® Quartus® Prime Pro Software: Chip Planner.
Signal Tap Logic Analyzer: Basic Configuration & Trigger Conditions.
Introduction to Kafka™.
Introduction to High Performance Computing (HPC).
Introduction to Apache™ Hadoop.
Design Evaluation for Timing Closure.
Introduction to Apache Spark™.
Introduction to Deep Learning.
Building Custom Platforms for Intel® FPGA SDK for OpenCL™: BSP Basics.
Building Custom Platforms for Intel® FPGA SDK for OpenCL™: Modifying a Reference Platform.
Getting Started with the Intel® Distribution of OpenVINO™ toolkit with FPGAs.
Low-Density Parity-Check (LDPC) Codes Intel® FPGA IP for 5G Systems.
University Workshop: Introduction to Simulation and Debug of FPGAs.
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Power Analyzer.
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Intro & Early Power Estimator.
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: Optimization.
Power Analysis & Optimization for Intel Arria 10 & Stratix 10 Devices: SmartVoltage ID.
Design Block Reuse in the Intel® Quartus® Prime Pro Software.
Performance Tuning Architectures with the Intel® FPGA Deep Learning Acceleration Suite.
Incremental Block-Based Compilation in the Intel Quartus® Prime Pro Software: Introduction.
Incremental Block-Based Compilation in the Intel Quartus® Prime Pro Software: Design Partitioning.
Getting started with Intel PAC with Intel A10 GX FPGA.
Introduction to the Intel® FPGA P-Tile.
Intel® Hyperflex™ Architecture Overview for Intel Agilex™ Devices.
Configuring the Intel® FPGA E-Tile Hard IP for Ethernet.
Intel® FPGA E-Tile Clocking.
Intel® Agilex™ FPGAs Fabric Improvements.
Getting Started with Linux* OS for Intel® SoC FPGAs.
Introduction to Hyper-Pipelining.
Building an Accelerator Functional Unit for the Intel® FPGA Programmable Acceleration Card N3000.
Reducing Compile Time with Fast Preservation.
Introduction to Memory Interfaces in Intel® Agilex™ Devices.
Integration of Memory Interfaces in Intel® Agilex™ Devices.
What’s New in 20.1?.
Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller.
Verifying Memory Interfaces in Intel® Agilex™ Devices.
On-Chip Debugging of Memory Interfaces in Intel® Agilex™ Devices.
Intel® Quartus® Prime Software Hyper-Aware Design Flow.
Introduction to Hyper-Optimization.
Introduction to Intel® FPGA Programmable Acceleration Card N3000.
Eliminating Barriers to Hyper-Retiming.
Intel® Agilex FPGA Configuration.
Open Programmable Acceleration Engine (OPAE) In Depth.
Designing Boards with Intel® Agilex™ FPGAs.
Introduction to Hyper-Retiming.
Incremental Block-Based Compilation in the Intel Quartus® Prime Pro Software: Timing Closure & Tips.
Timing Analyzer: Introduction to Timing Analysis.
Timing Analyzer: Timing Analyzer GUI.
Timing Analyzer: Intel® Quartus® Prime Software Integration & Reporting.
Timing Analyzer: Required SDC Constraints.
Debugging with the Ethernet Toolkit.
Intel® Stratix® 10 FPGA L- and H-Tile Transceiver Basics.
Intel FPGA Power and Thermal Calculator for Intel FPGA Devices.
Understanding Timing Analysis in FPGAs.
Platform Designer Standard Interfaces.
Reset Methodology.
Using Fast Forward Compile for the Intel® HyperFlex™ Architecture.
Clock Domain Crossing Considerations.
Intel® Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer.
Intel® Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections.
Intel® Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints.
Intel® Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces.
Intel® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions.
eCPRI Intel® FPGA IP: Getting Started.
eCPRI Intel® FPGA IP: Architecture and Interfaces.
eCPRI Intel® FPGA IP: Customizing the IP.

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Intel FPGA

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