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Digital Electronic Circuits
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Digital Electronic Circuits
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- 1 Digital Electronic Circuits
- 2 Lecture 01: Introduction
- 3 Lecture 02: Transistor as a Switch
- 4 Lecture 03 : Performance Issue and Introduction to TTL
- 5 Lecture 04 : Transistor Transistor Logic (TTL)
- 6 Lecture 05: CMOS Logic
- 7 Lecture 06: Basic Gates and their representations
- 8 Lecture 07 : Fundamentals of Boolean Algebra
- 9 Lecture 08 : Boolean Function to Truth Table and Implementation Issues
- 10 Lecture 09 : Truth Table to Boolean Function and Implementation Issues
- 11 Lecture 10 : Karnugh Map and Digital Circuit Realization
- 12 Lecture 11: Karnaugh Map to Entered Variable Map
- 13 Lecture 12: Quine - McClusky (QM) Algorithm
- 14 Lecture 13: Cost Criteria and Minimization of Multiple Output Functions
- 15 Lecture 14: Static 1 Hazard
- 16 Lecture 15: Static 0 Hazard and Dynamic Hazard
- 17 Lecture 17: Multiplexer: Part II
- 18 Lecture 18: Demultiplexer / Decoder
- 19 Lecture 19: Decoder with BCD Input and Encoder
- 20 Lecture 16: Multiplexer: Part I
- 21 Lecture 20: Parity Generator and Checker
- 22 Lecture 21:Number System
- 23 Lecture 22: Negative Number and 2's Complement Arithmetic
- 24 Lecture 23: Arithmetic Building Blocks-I
- 25 Lecture 24: Arithmetic Building Blocks-II
- 26 Lecture 25: Overflow Detection and BCD Arithmetic
- 27 Lecture 26: Magnitude Comparator
- 28 Lecture 27: Arithmetic Logic Unit (ALU)
- 29 Lecture 28: Unweighted Code
- 30 Lecture 29: Error Detection and Correction Code
- 31 Lecture 30: Multiplication and Division
- 32 Lecture 31: SR Latch and Introduction to Clocked Flip-Flop
- 33 Lecture 32: Edge-Triggered Flip-Flop
- 34 Lecture 33: Representations of Flip-Flops
- 35 Lecture 34: Analysis of Sequential Logic Circuit
- 36 Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing Parameters
- 37 Lecture 36: Register and Shift Register: PIPO and SISO
- 38 Lecture 37: Shift Register: SIPO, PISO and Universal Shift Register
- 39 Lecture 38: Application of Shift Register
- 40 Lecture 39: Linear Feedback Shift Register
- 41 Lecture 40: Serial Addition, Multiplication and Division
- 42 Lecture 41: Asynchronous Counter
- 43 Lecture 42: Decoding Logic and Synchronous Counter
- 44 Lecture 44: Counter Design with Asynchronous Reset and Preset
- 45 Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of Counter
- 46 Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter
- 47 Lecture 46: Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model
- 48 Lecture 47: Moore Model and Mealy Model: Realization of Digital Logic Circuit
- 49 Lecture 48: Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic Circuit
- 50 Lecture 49: Circuit Realization from ASM Chart and State Minimization
- 51 Lecture 50: State Minimization by Implication Table and Partitioning Method
- 52 Lecture 51: Digital to Analog Conversion - I
- 53 Lecture 52: Digital to Analog Conversion - II
- 54 Lecture 55: Certain Performance Issue of ADC and DAC
- 55 Lecture 56: Introduction to Memory
- 56 Lecture 58: Dynamic RAM(DRAM) and Memory Expansion
- 57 Lecture 57: Static Random Access Memory (SRAM)
- 58 Lecture 59: Read Only Memory (ROM)
- 59 Lecture 60: PAL, PLA, CPLD, FPGA
- 60 Lecture 54: Analog to Digital Conversion - II
- 61 Lecture 53: Analog to Digital Conversion - I
