Overview of VLSI Design Flow - VI: Chip Manufacturing Process from Layout to Packaging

This lecture provides a comprehensive overview of the post-layout manufacturing processes in VLSI chip production. Learn about the critical steps that occur after obtaining the GDS layout, including mask fabrication, front end of the line (FEOL) processes, back end of the line (BEOL) processes, die testing, and packaging. Explore the importance of advanced techniques for modern semiconductor manufacturing such as resolution enhancement techniques (RET), optical proximity correction (OPC), and multi-patterning methodologies that are essential for advanced process nodes. Gain insights into the complete chip manufacturing workflow in this 29-minute presentation from NPTEL-NOC IITM.