Explore the fundamentals of VLSI design flow from RTL to GDS in this introductory video lecture presented by Prof. Sneh Saurabh from the Electronics and Communication Engineering department at IIIT Delhi. Gain insights into the course structure and key concepts that will be covered throughout the program, providing a solid foundation for understanding the intricate process of transforming Register Transfer Level (RTL) designs into final chip layouts using GDSII format.
VLSI Design Flow: RTL to GDS - Course Introduction
Overview
Syllabus
VLSI Design Flow: RTL to GDS - Course Intro
Taught by
NPTEL-NOC IITM
