Digital System Design with PLDs and FPGAs

Digital System Design with PLDs and FPGAs

nptelhrd via YouTube Direct link

Mod-01 Lec-01 Course Contents, Objective

1 of 44

1 of 44

Mod-01 Lec-01 Course Contents, Objective

Class Central Classrooms beta

YouTube videos curated by Class Central.

Classroom Contents

Digital System Design with PLDs and FPGAs

Automatically move to the next video in the Classroom when playback concludes

  1. 1 Mod-01 Lec-01 Course Contents, Objective
  2. 2 Mod-01 Lec-02 Revision of Prerequisite
  3. 3 Mod-01 Lec-03 Design of Synchronous Sequential Circuits
  4. 4 Mod-02 Lec-04 Analysis of Synchronous Sequential Circuits
  5. 5 Mod-02 Lec-05 Top-down Design
  6. 6 Mod-02 Lec-06 Controller Design
  7. 7 Mod-02 Lec-07 Control algorithm and State diagram
  8. 8 Mod-02 Lec-08 Case study 1
  9. 9 Mod-03 Lec-09 Entity, Architecture and Operators
  10. 10 Mod-03 Lec-10 Concurrency, Data flow and Behavioural models
  11. 11 Mod-03 Lec-11 Structural Model, Simulation
  12. 12 Mod-03 Lec-12 Simulating Concurrency
  13. 13 Mod-03 Lec-13 Classes and Data types
  14. 14 Mod-03 Lec-14 Concurrent statements and Sequential statements
  15. 15 Mod-03 Lec-15 Sequential statements and Loops
  16. 16 Mod-03 Lec-16 Modelling flip-flops, Registers
  17. 17 Mod-03 Lec-17 Synthesis of Sequential circuits
  18. 18 Mod-03 Lec-18 Libraries and Packages
  19. 19 Mod-03 Lec-19 Operators, Delay modelling
  20. 20 Mod-03 Lec-20 Delay modelling
  21. 21 Mod-03 Lec-21 VHDL Examples
  22. 22 Mod-04 Lec-22 VHDL Examples, FSM Clock
  23. 23 Mod-02 Lec-23 FSM issues 1
  24. 24 Mod-02 Lec-24 FSM Issues 2
  25. 25 Mod-02 Lec-25 FSM Issues 3
  26. 26 Mod-03 Lec-26 VHDL coding of FSM
  27. 27 Mod-02 Lec-27 FSM Issues 4
  28. 28 Mod-02 Lec-28 FSM Issues 5
  29. 29 Mod-02 Lec-29 Synchronization 1
  30. 30 Mod-02 Lec-30 Synchronization 2
  31. 31 Mod-05 Lec-31 Evolution of PLDs
  32. 32 Mod-02 Lec-32 Simple PLDs
  33. 33 Mod-05 Lec-33 Simple PLDs: Fitting
  34. 34 Mod-05 Lec-34 Complex PLDs
  35. 35 Mod-06 Lec-35 FPGA Introduction
  36. 36 Mod-06 Lec-36 FPGA Interconnection, Design Methodology
  37. 37 Mod-06 Lec-37 Xilinx Virtex FPGA’s CLB
  38. 38 Mod-06 Lec-38 Xilinx Virtex Resource Mapping, IO Block
  39. 39 Mod-06 Lec-39 Xilinx Virtex Clock Tree
  40. 40 Mod-06 Lec-40 FPGA Configuration
  41. 41 Mod-06 Lec-41 Altera and Actel FPGAs
  42. 42 Mod-03 Lec-42 VHDL Test bench
  43. 43 Mod-02 Lec-43 Case study 2
  44. 44 Mod-02 Lec-44 Case study on FPGA Board

Never Stop Learning.

Get personalized course recommendations, track subjects and courses with reminders, and more.

Someone learning on their laptop while sitting on the floor.