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Stanford University


Stanford University via Stanford OpenEdx

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We are all too familiar with our iPhones, iPads, and other smartphones and tablets that we use every day. Have you ever wondered what are the chips and components inside them? how much they cost? And how they are manufactured? In this course we will learn about ‘Nanomanufacturing’ which is the underlying technology to make the different semiconductor chips and components that enable these devices.

We will ponder upon issues like: how the post-PC era is changing the semiconductor industry? What’s ailing Moore’s law? I will combine my experience from teaching this course at Stanford and my work in the industry to make you aware of the ‘state of art’ in the semiconductor and display industry. We will have lots of fun too! I will take you on field trips where you can check out some of the action with me.

What we will cover in each of the 6 weeks is described in more details below; if that piques your interest, please sign up. I look forward to seeing you in class!


Week 1: LCD and OLED Displays 
We will detail on the nanomanufacturing steps involved in making a start of art LCD/TFT display. We will answer questions like why making high resolution displays such as Apple’s retina display requires moving all the circuitry to the back? What’s needed to make a display which is readable in sunlight? To reduce its power consumption? We will also cover the new technologies like: OLEDs, oxide based transistors etc. that point to a BRIGHT future in the field of display technology.

Week 2: Lithography and Patterning 
Lithography is the most expensive part of fabricating a chip today and many believe that it might be the Achilles’ heel which brings to an end the cost saving achieved by Moore’s law. Moreover the way we achieve smallest feature sizes using a given lithography source is continuously changing. In this part we will discuss evolutionary solutions such as double patterning, quad patterning, and things on the horizon such as EUV, and also revolutionary solutions such as direct printing, self-assembly etc.

Week 3: Process Technology and Moore's Law 
We will spend time on developing the fundamentals of process technology and how the different process steps are combined together to make a logic or a memory chips. We will classify the processes as additive vs. substantive and also as line-of-sight vs. conformal. We will also look at Moore's law and see what is ailing it today.

Week 4: FinFETs 
In this section we will discuss the various nanomanufacturing steps involved in making a start of art microprocessor. Process technology for FinFETS will be described.

Week 5: Flash memory
We will discuss the various nanomanufacturing steps involved in making a start of art flash memory chips which are ubiquitous in smartphones, tablets and solid state drives today. Discuss recent trends such as 3D NAND etc.

Week 6: Packaging and 3D ICs 
We will discuss the advantages and challenges of integrating chips made using different processes and achieving different functionality into a single monolithic package. We will explain how nanomanufacturing technology is enabling things like interposers (2.5D), through silicon via (TSV), microbump etc.

Taught by

Aneesh Nainani


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