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Mod-01 Lec-34 Effect of Clock Jitter on CTDSMs - 1
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Classroom Contents
VLSI Data Conversion Circuits
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- 1 Mod-01 Lec-01 Introduction to Data Conversion
- 2 Mod-01 Lec-02 Sampling-1
- 3 Mod-01 Lec-03 Sampling-2
- 4 Mod-01 Lec-04 Nonidealities in Samples
- 5 Mod-01 Lec-05 Noise due to Sampling
- 6 Mod-01 Lec-06 Distortion in a Sampling Switch
- 7 Mod-01 Lec-07 Gate Boosted Switches-1
- 8 Mod-01 Lec-08 Gate Boosted Switches-2
- 9 Mod-01 Lec-09 Charge Injection
- 10 Mod-01 Lec-10 S/H Characterization - 1
- 11 Mod-01 Lec-11 S/H Characterization - 2
- 12 Mod-01 Lec-12 FFTs and Leakage
- 13 Mod-01 Lec-13 Spectral Windows - 1
- 14 Mod-01 Lec-14 Spectral Windows-2
- 15 Mod-01 Lec-15 ADC/DAC Definitions
- 16 Mod-01 Lec-16 Quantization Noise - I
- 17 Mod-01 Lec-17 Quantization Noise -2
- 18 Mod-01 Lec-18 Oversampling & Noise Shaping
- 19 Mod-01 Lec-19 Delta-Sigma Modulation - 1
- 20 Mod-01 Lec-20 Delta-Sigma Modulation - 2
- 21 Mod-01 Lec-21 Linearized Analysis
- 22 Mod-01 Lec-22 Stability of Delta Sigma Modulators
- 23 Mod-01 Lec-23 High Order DSMs
- 24 NTF Design and Tradeoffs
- 25 Mod-01 Lec-25 Single bit Modulators
- 26 Loop Filter Architectures
- 27 Mod-01 Lec-27 Continous-time Delta Sigma Modulation
- 28 Mod-01 Lec-28 Implicit Antialiasing
- 29 Mod-01 Lec-29 Modulators with NRZ and Impulsive DACs
- 30 Mod-01 Lec-30 High Order CTDSMs
- 31 Mod-01 Lec-31 CTDM Design
- 32 Mod-01 Lec-32 Excess Loop Delay (ELD)
- 33 Mod-01 Lec-33 ELD Compensation
- 34 Mod-01 Lec-34 Effect of Clock Jitter on CTDSMs - 1
- 35 Mod-01 Lec-35 Effect of Clock Jitter on CTDSMs - 2
- 36 Mod-01 Lec-36 Dynamic Range Scaling
- 37 Mod-01 Lec-37 Simulation of CTDSMs
- 38 Mod-01 Lec-38 Integrator Design-1
- 39 Mod-01 Lec-39 Integrator Design-2
- 40 Mod-01 Lec-40 Flash ADC Design
- 41 Mod-01 Lec-41 Latches and Metastability
- 42 Mod-01 Lec-42 Offset in a Latch-1
- 43 Mod-01 Lec-43 Offset in a Latch-2 Auto Zeroing
- 44 Mod-01 Lec-44 Auto Zeroing-2
- 45 Mod-01 Lec-45 Auto Zeroing-3
- 46 Mod-01 Lec-46 Autozeroing in Flash ADCs
- 47 Mod-01 Lec-47 Flash ADC Case Study
- 48 Mod-01 Lec-48 Flash ADC Case Study
- 49 Mod-01 Lec-49 Flash ADC in a Delta Sigma Loop
- 50 Mod-01 Lec-50 DAC Basics
- 51 Mod-01 Lec-51 Binary and Thermometer DACs
- 52 Mod-01 Lec-52 Segmented DACs
- 53 Mod-01 Lec-53 Optimal DAC Segmentation
- 54 Mod-01 Lec-54 DAC Nonlinearities
- 55 Mod-01 Lec-55 Current Steering DACs-1
- 56 Mod-01 Lec-56 Current Steering DACs-2
- 57 Mod-01 Lec-57 DAC Mismatches in DSMs
- 58 Mod-01 Lec-58 Calibration and Randomization
- 59 Mod-01 Lec-59 Dynamic Element Matching-1
- 60 Mod-01 Lec-60 Dynamic Element Matching-2
