Inter VM Data Exfiltration - The Art of Cache Timing Covert Channel on x86 Multi-Core

Inter VM Data Exfiltration - The Art of Cache Timing Covert Channel on x86 Multi-Core

NorthSec via YouTube Direct link

Intro

1 of 40

1 of 40

Intro

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Inter VM Data Exfiltration - The Art of Cache Timing Covert Channel on x86 Multi-Core

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  1. 1 Intro
  2. 2 Cache Timing Covert Channel
  3. 3 Disclaimer
  4. 4 The problem
  5. 5 I was caught
  6. 6 I did a video
  7. 7 Outline of the talk
  8. 8 Shared resources
  9. 9 Multiple socket
  10. 10 Cache line
  11. 11 Cache timing modulation
  12. 12 Demo
  13. 13 Test Program
  14. 14 Test Results
  15. 15 BIOS Prefetcher
  16. 16 Solution
  17. 17 Userspace
  18. 18 Physical Address
  19. 19 KSM
  20. 20 No synchronization primitive
  21. 21 Phase lock loop
  22. 22 CLflush
  23. 23 The Client
  24. 24 Monotonic Pulse
  25. 25 Timers
  26. 26 Jitter
  27. 27 Compensation
  28. 28 Results
  29. 29 Synchronization
  30. 30 Recap
  31. 31 Original experiment
  32. 32 CPU usage
  33. 33 Reverse shell example
  34. 34 Forward error correction
  35. 35 ReedSolomon
  36. 36 Reverse Shell
  37. 37 Disable KSM
  38. 38 Disable CL Flourish
  39. 39 Where Counters
  40. 40 Heuristic

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