This course is for anyone passionate in learning how to develop FPGA-accelerated applications with SDAccel!
We are entering in an era in which technology progress induces paradigm shifts in computing!
As a tradeoff between the two extreme characteristics of GPP and ASIC, we can find a new concept, a new idea of computing... the reconfigurable computing, which has combined the advantages of both the previous worlds. Within this context, we can say that reconfigurable computing will widely, pervasively, and gradually impact human lives. Hence, it is time that we focus on how reconfigurable computing and reconfigurable system design techniques are to be utilised for building applications.
One one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance.
Within this context, the Xilinx SDx tools, including the SDAccel environment, the SDSoC environment, and Vivado HLS, provide an out-of-the-box experience for system programmers looking to partition elements of a software application to run in an FPGA-based hardware element, and having that hardware work seamlessly with the rest of the application running in a processor or embedded processor.
The out-of-the-box experience will provide interesting and, let us say, “good enough” results for many applications.
However, this may not be true for you, you may be looking for better performance, data throughput, reduced latency, or to reduce the resources usage... This course is focusing exactly on this. After introducing you to the FPGAs we are going to dig more into the details on how to use Xilinx SDAccel providing you also with working examples on how to optimize the hardware logic to obtain the best of of your hardware implementations. In this case, certain attributes, directives, or pragmas, can be used to direct the compilation and synthesis of the hardware kernel, or to optimise the function of the data mover operating between the processor and the hardware logic.
Furthermore, In this course we are going to focus on distributed, heterogeneous infrastructures, presenting how to bring your solutions to life by using the Amazon EC2 F1 instances.
Familizarize youself with FPGA technologies
From the mid-1980s, reconfigurable computing has become a popular field due to the FPGA technology progress. An FPGA is a semiconductor device containing programmable logic components and programmable interconnects but no instruction fetch at run time, that is, FPGAs do not have a program counter. In most FPGAs, the logic components can be programmed to duplicate the functionality of basic logic gates or functional Intellectual Properties (IPs). FPGAs also include memory elements composed of simple flip-flops or more complex blocks of memories. Hence, FPGA has made possible the dynamic execution and configuration of both hardware and software on a single chip. This module provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.
A bird's eye view on SDAccel
The Xilinx SDAccel Development Environment let the user express kernels in OpenCL C, C++ and RTL (as an example we can think of, SystemVerilog, Verilog or VHDL) to run on Xilinx programmable platforms. The programmable platform is composed of (1) the SDAccel Xilinx Open Code Compiler (XOCC), (2) a Device Support Archive (DSA) which describes the hardware platform, (3) a software platform, (4) an accelerator board, and5. last but not least, the SDAccel OpenCL runtime. Within this module, after an introduction to OpenCL, we are going to see how this language has been sued in SDAccel and the main "components" of this toolchain.
On how to optmize your system
Within this module, Before getting into the optimisation, we will first understand how an FPGA is working, also from a computational point of view. Although the traditional FPGA design flow is more similar to a regular IC than a processor, an FPGA provides significant cost advantages in comparison to an IC development effort and offers the same level of performance in most cases. Another advantage of the FPGA when compared to the IC is its ability to be dynamically reconfigured. This process, which is the same as loading a program in a processor, can affect part or all of the resources available in the FPGA fabric. When compared with processor architectures, the structures that comprise the FPGA fabric enable a high degree of parallelism in application execution. The custom processing architecture generated by SDAccel for an OpenCL kernel presents a different execution paradigm. This must be taken into account when deciding to port an application from a processor to an FPGA. To better understand such a scenario we will briefly compare a processor sequential execution with the intrinsic parallel nature of an FPGA implementation.
Furthermore, within this module we are going to familiarise ourselves with the application optimisation flow.The Xilinx SDAccel Environment is a complete Software Development Environment, for creating, compiling, and optimising OpenCL applications with the objective of being accelerated on Xilinx FPGAs. From a designer perspective we can organise the flow for optimising an application in the SDAccel Environment as a three phases flow. Those three phases are: (1) baselining functionalities and performance, (2) optimising data movement and (3) optimising kernel computation
Optimize your system via SDAccel
In this module we will provide a bird's eye view on the available SDAccel optimisations.
The presented optimisations are not the only available ones, but they are more a list of recommendations to optimise the performance of an OpenCL application that have to be used as a starting point for ideas to consider or investigate further. Within this context we will organise these “recommendations” in three sets of optimisations: (1) arithmetic optimisations, (2) data-related optimisations, and finally (3) memory-related optimisations.
After an overall description of possibile optimisations, within this module we will focus on four specific optimisations (1) loop unrolling, (2) loop pipelining, (3) array partitioning and (4) the host optimisations. First, we will describe loop unrolling which means to unroll the loop iterations so that, the number of iterations of the loop reduces, and the loop body performs extra computation. This technique allows to expose additional instruction level parallelism that Vivado HLS can exploit to implement the final hardware design. After that we will present the loop pipelining optimisation, where we will move from a sequential execution of the loop iterations to a pipelined execution in which the loop iterations are overlapped in time. After that we will present the array partitioning optimisation which allows to optimise the usage of BRAM resources in order to improve the performance of the kernel. Finally, at the end of this module we are going to discuss optimisations related to the host system that is responsible for transferring the data to and from the FPGA board, as well as to send the command to start the execution of a kernel.
An introduction to FPGA-augmented cloud infrastructures