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Digital Electronics

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Syllabus

What is Signal?.
What is an Analog Signal?.
What is Digital Signal?.
Need of Digital Signals.
Introduction to Digital Electronics.
Switch and Bits Intuition.
Introduction to Boolean Algebra (Part 1).
Introduction to Boolean Algebra (Part 2).
Boolean Algebra Examples (Part 1).
Boolean Algebra Examples (Part 2).
Redundancy Theorem (Boolean Algebra Trick).
Sum of Products (Part 1) | SOP Form.
Sum of Products (Part 2) | SOP Form.
Product of Sums (Part 1) | POS Form.
Product of Sums (Part 2) | POS Form.
SOP and POS Form Examples.
Minimal to Canonical Form Conversion (Part 1).
Minimal to Canonical Form Conversion (Part 2).
Examples & Tricks (SOP and POS Forms).
Positive and Negative Logic.
Dual Form.
Self Dual.
Complement Meaning and Examples.
Venn Diagram.
Switching Circuits (Part 1).
Switching Circuits (Part 2).
Statement Problems in Boolean Algebra (Part 1).
Statement Problems in Boolean Algebra (Part 2).
Introduction to Number Systems.
Binary Number System.
Decimal to Binary Conversion.
Decimal to Octal Conversion.
Decimal to Hexadecimal Conversion.
Binary to Decimal Conversion.
Octal to Decimal Conversion.
Hexadecimal to Decimal Conversion.
Octal to Binary & Binary to Octal Conversion.
Hexadecimal to Binary & Binary to Hexadecimal Conversion.
Hexadecimal to Octal & Octal to Hexadecimal Conversion.
Binary Addition.
Binary Subtraction.
Binary Multiplication.
Binary Division.
Octal Addition.
Octal Subtraction.
Octal Multiplication.
Hexadecimal Addition.
Hexadecimal Subtraction.
Hexadecimal Multiplication.
r's Complement.
(r-1)'s Complement.
1's and 2's Complement.
Shortcut for 2's Complement.
Data Representation using Signed Magnitude.
Data Representation using 1's Complement.
Data Representation using 2's Complement.
Binary Subtraction using 1's Complement.
Binary Subtraction using 2's Complement.
Classification of Codes.
Binary Coded Decimal (BCD) Code.
BCD Addition.
Shift Add 3 Method | Simple method for Binary to BCD conversion.
2421 Code.
Excess-3 Code (XS-3 Code).
Excess-3 Code Addition.
Introduction to Gray Code.
Binary to Gray Code Conversion.
Gray Code to Binary Conversion.
What is Parity?.
Hamming Code | Error detection.
Hamming Code | Error Correction.
Logic Gates (Part 1).
Logic Gates (Part 2).
Logic Gates (Part 3).
Logic Gates (Part 4).
Logic Gates (Part 5) | Important!.
Logic Gates (Part 6) | Important!.
NAND Gate as Universal Gate (Part 1).
NAND Gate as Universal Gate (Part 2).
NOR Gate as Universal Gate.
Karnaugh Map (K' Map) - Part 1.
Karnaugh Map (K' Map) - Part 2.
Karnaugh Map (K' Map) - Part 3.
K' Map and Implicants.
4 Variable Karnaugh Map (Part 1).
4 Variable Karnaugh Map (Part 2).
4 Variable Karnaugh Map (Part 3).
Don't Care in Karnaugh Map (K' Map).
Don't Care in K' Map (Response to Doubt).
K' Map using Max Terms (Part 1).
K' Map using Max Terms (Part 2).
5 variables K' Map.
Quine-McCluskey Minimization Technique (Tabular Method).
Digital Electronics Previous Year Solution of DRDO & ISRO (Part 2).
Digital Electronics Previous Year Solution of DRDO & ISRO (Part 3).
4-Bit Even Parity Generator.
Seven Segment Display Decoder.
Seven Segment Display Decoder (Part 2).
Seven Segment Display Decoder (Part 3).
Comparison between Combinational and Sequential Circuits.
Half Adder.
Full Adder.
Full Adder using Half Adder.
4 Bit Parallel Adder using Full Adders.
Half Subtractor.
Full Subtractor | Easy Explanation.
Realizing Half Adder using NAND Gates only.
Realizing Half Adder using NOR Gates only.
Realizing Full Adder using NAND Gates only.
Realizing Half Subtractor using NAND Gates only.
Realizing Half Subtractor using NOR Gates only.
Realizing Full Subtractor using NAND Gates only (Part 1).
Realizing Full Subtractor using NAND Gates only (Part 2).
2-Bit Multiplier Using Half Adders.
Carry Lookahead Adder (Part 1) | CLA Generator.
Carry Lookahead Adder (Part 2) | CLA Adder.
BCD Adder | Simple Explanation.
Introduction to Multiplexers | MUX Basic.
4X1 Multiplexer.
8X1 Multiplexer.
MUX Tree Basic | 4X1 MUX using 2X1 MUX | Easy Explanation.
Implementing 8X1 MUX using 2X1 MUX.
Implementing 8X1 MUX using 4X1 MUX (Special Case).
32X1 MUX using 8X1 MUX.
Implementation of Boolean Function using Multiplexers.
1-Bit Full Adder using Multiplexer.
Logical Expression from Multiplexer.
Introduction to Demultiplexer | 1:2 DEMUX.
1:4 Demultiplexer.
Full Subtractor using 1:8 Demultiplexer.
Demultiplexer as Decoder.
2-Bit Comparator.
Introduction to Encoders and Decoders.
Priority Encoder.
Decimal to BCD Encoder.
Octal to Binary Encoder.
Hexadecimal to Binary Encoder.
Full Adder Implementation using Decoder.
Practice Problems on Combinational Circuits (Part 1).
Practice Problems on Combinational Circuits (Part 2).
Practice Problems on Combinational Circuits (Part 3).
Practice Problems on Combinational Circuits (Part 4).
Digital Electronics Test-1.
Introduction to Sequential Circuits | Important.
SR Latch | NOR and NAND SR Latch.
What is a Clock?.
Triggering Methods in Flip Flops.
How to get Edge Triggering | Simulation using Multisim.
Difference between Latch and Flip Flop.
Introduction to SR Flip Flop.
Truth Table, Characteristic Table and Excitation Table for SR Flip Flop.
Introduction to D flip flop.
Truth Table, Characteristic Table and Excitation Table for D Flip Flop.
Introduction to JK flip flop.
Truth Table, Characteristic Table and Excitation Table for JK flip flop.
Race Around Condition or Racing in JK Flip Flop.
Master Slave JK Flip Flop.
Behaviour of Master Slave D Flip Flop.
Introduction to T flip flop.
Truth Table, Characteristic Table and Excitation Table for T flip flop.
5 Steps for Flip Flop Conversions | JK to D Flip Flop Conversion.
T Flip Flop to D Flip Flop Conversion.
SR Flip Flop to JK Flip Flop Conversion.
SR Flip Flop to T Flip Flop Conversion.
Preset and Clear Inputs in Flip Flop.
Introduction to State Table, State Diagram & State Equation.
Design Procedure for Clocked Sequential Circuits.
Mealy and Moore State Machines (Part 1).
Mealy and Moore State Machines (Part 2).
Analysis of Clocked Sequential Circuits (with D Flip Flop).
Analysis of Clocked Sequential Circuits (with JK Flip Flop).
Analysis of Clocked Sequential Circuits (with T Flip Flop).
Sequence or Pattern Detector.
Sequence Detector (Example).
State Reduction and Assignment.
ASM Chart.
ASM Chart for Moore State Machine.
Difference between Synchronous and Asynchronous Sequential Circuits.
Introduction to Counters | Important.
Types of Counters | Comparison between Ripple and Synchronous counters.
3 Bit Asynchronous Up Counter.
4 Bit Asynchronous Up Counter.
3 bit & 4 bit Asynchronous Down Counter.
3 Bit & 4 Bit UP/DOWN Ripple Counter.
Modulus of the Counter & Counting up to Particular Value.
State Diagram of a Counter.
Decade (BCD) Ripple Counter.
How to Design Synchronous Counters | 2-Bit Synchronous Up Counter.
3-Bit Synchronous Up Counter.
3-Bit & 4-bit Up/Down Synchronous Counter.
Ring Counter.
Johnson's Counter (Twisted/Switch Tail Ring Counter).
Introduction to Registers.
Data Formats and Classification of Registers.
Shift Register (SISO Mode).
Shift Register (SIPO & PIPO Mode).
Shift Register (PISO Mode).
Bidirectional Shift Register.
Universal Shift Register.
Practice Problems on Sequential Circuits (Part 2).
Practice Problems on Sequential Circuits (Part 3).
Programmable Logic Array (PLA) | Easy Explanation.
Programmable Array Logic (PAL).

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