Learn to design a Finite Impulse Response (FIR) filter for Field-Programmable Gate Arrays (FPGAs) using Xilinx Vivado High Level Synthesis in just 30 minutes. The course covers designing the filter in C, programming it, and adjusting filter coefficients. The teaching method involves practical examples and demonstrations. This course is intended for individuals interested in FPGA development and digital signal processing.
Overview
Syllabus
Introduction
Basic ISE project
Start HLS project
FPGA FIR filter design
Reprogram FPGA
Filter coefficients
Taught by
Colin O'Flynn
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