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NPTEL

Electronics - Advanced VLSI Design

NPTEL and Indian Institute of Technology Bombay via YouTube

Overview

Instructors: Prof. A. N. Chandorkar, Prof. D. K. Sharma, Prof. Sachin Patkar, and Prof. Virendra K. Singh, Department of Electrical Engineering, IIT Bombay.

This course covers topics in VLSI design: Historical perspective of VLSI, CMOS VLSI design for power and speed consideration, Logical effort, Designing fast CMOS circuits, Datapath design, Interconnect aware design, Hardware description Languages for VLSI design, FSM controller/datapath and processor design, VLSI design automation, and VLSI design test and verification.

Syllabus

Mod-01 Lec-01 Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design.
Mod-01 Lec-02 Historical Perspective and Future Trends in CMOS VLSI Circuit -Part II.
Mod-01 Lec-03 Logical Effort - A way of Designing Fast CMOS Circuits.
Mod-01 Lec-04 Logical Effort - A way of Designing Fast CMOS Circuits continued.
Mod-01 Lec-05 Logical Effort - A way of Designing Fast CMOS Circuits -Part III.
Mod-01 Lec-06 Power Estimation and Control in CMOS VLSI circuits.
Mod-01 Lec-07 Power Estimation and Control in CMOS VLSI circuits continued.
Mod-01 Lec-08 Low Power Design Techniques.
Mod-01 Lec-09 Low Power Design Techniques -Part II.
Mod-01 Lec-10 Arithmetic Implementation Strategies for VLSI.
Mod-01 Lec-11 Arithmetic Implementation Strategies for VLSI -Part II.
Mod-01 Lec-12 Arithmetic Implementation Strategies for VLSI -Part III.
Mod-01 Lec-13 Arithmetic Implementation Strategies for VLSI -Part IV.
Mod-01 Lec-14 Interconnect aware design: Impact of scaling, buffer insertion and inductive peaking.
Mod-01 Lec-15 Interconnect aware design: Low swing and Current Mod-e signaling.
Mod-01 Lec-16 Interconnect aware design: capacitively coupled interconnects.
Mod-01 Lec-17 Introduction to Hardware Description Languages.
Mod-01 Lec-18 Managing concurrency and time in Hardware Description Languages.
Mod-01 Lec-19 Introduction to VHDL.
Mod-01 Lec-20 Basic Components in VHDL.
Mod-01 Lec-21 Structural Description in VHDL.
Mod-01 Lec-22 Behavioral Description in VHDL.
Mod-01 Lec-23 Introduction to Verilog.
Mod-01 Lec-24 FSM + datapath (GCD example).
Mod-01 Lec-25 FSM + datapath (continued).
Mod-01 Lec-26 Single Cycle MMIPS.
Mod-01 Lec-27 Multicycle MMIPS.
Mod-01 Lec-28 Multicycle MMIPS â FSM.
Mod-01 Lec-29 Brief Overview of Basic VLSI design Automation Concepts.
Mod-01 Lec-30 Netlist and System Partitioning.
Mod-01 Lec-31 Timing Analysis in the context of Physical design Automation.
Mod-01 Lec-32 Placement algorithm.
Mod-01 Lec-33 Introduction to VLSI Testing.
Mod-01 Lec-34 VLSI Test Basics - I.
Mod-01 Lec-35 VLSI Test Basics - II.
Mod-01 Lec-36 VLSI Testing: Automatic Test Pattern Generation.
Mod-01 Lec-37 VLSI Testing: design for Test (DFT).
Mod-01 Lec-38 VLSI Testing: Built-in Self-Test (BIST).
Mod-01 Lec-39 VLSI design Verification: An Introduction.
Mod-01 Lec-40 VLSI design Verification: An Introduction.
Mod-01 Lec-41 VLSI design Verification: Equivalence/Model Checking.
Mod-01 Lec-42 VLSI design Verification: Model Checking.

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