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NPTEL

Embedded Systems - Design Verification and Test

NPTEL and Indian Institute of Technology Guwahati via YouTube

Syllabus

Embedded Systems - Design Verification and Test [Introduction Video].
Introduction.
Modeling Techniques – 1.
Modeling Techniques – 2.
Hardware/Software Partitioning - 1.
Hardware/Software Partitioning - 2.
Introduction to Hardware Design.
Hardware Architectural Synthesis – 1.
Hardware Architectural Synthesis – 2.
Hardware Architectural Synthesis – 3.
Hardware Architectural Synthesis – 4.
Hardware Architectural Synthesis – 5.
Hardware Architectural Synthesis – 6.
Hardware Architectural Synthesis – 7.
System Level Analysis.
Uniprocessor Scheduling – 1.
Uniprocessor Scheduling – 2.
Multiprocessor Scheduling – 1.
Multiprocessor Scheduling – 2.
Introduction and Basic Operators of Temporal Logic.
Syntax and Semantics of CTL.
Equivalence between CTL formulas.
Model Checking Algorithm.
Binary Decision Diagram.
Use of OBDDs for State Transition System.
Symbolic Model Checking.
Introduction to Digital VLSI Testing.
Automatic Test Pattern Generation (ATPG).
Scan Chain based Sequential Circuit Testing.
Software-Hardware Co-validation Fault Models and High Level Testing for Complex Embedded Systems.
Testing for embedded cores.
Bus and Memory Testing.
Testing for advanced faults in Real time Embedded Systems.
BIST for Embedded Systems.
Concurrent Testing for Fault tolerant Embedded Systems - 1.
Concurrent Testing for Fault tolerant Embedded Systems - 2.
Testing for Reprogrammable hardware.
Interaction Testing between Hardware and Software.

Taught by

NPTEL IIT Guwahati

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