The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
Verilog, VHDL, and RTL design for FPGA and CPLD architectures
FPGA development tools flow: specify, synthesize, simulate, compile, program and debug
Configurable embedded processors and embedded software
Use of soft-core and hard-core processors and OS options
FPGA System engineering, software-hardware integration, and testing
IP development and incorporating 3rd-party IP
The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.
This course can also be taken for academic credit as ECEA 5360, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Programmable Logic has become more and more common as a core technology used to build electronic systems. By integrating soft-core or hardcore processors, these devices have become complete systems on a chip, steadily displacing general purpose processors and ASICs. In particular, high performance systems are now almost always implemented with FPGAs.
This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. You use FPGA development tools to complete several example designs, including a custom processor. If you are thinking of a career in Electronics Design or an engineer looking at a career change, this is a great course to enhance your career opportunities.
You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. The tools do not run on Apple Mac computers. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, or it may be possible to upgrade the memory.
This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.
This course will introduce you to all aspects of development of Soft Processors and Intellectual Property (IP) in FPGA design. You will learn the extent of Soft Processor types and capabilities, how to make your own Soft Processor in and FPGA, including how to design the hardware and the software for a Soft Processor. You will learn how to add IP blocks and custom instructions to your Soft Processor. After the Soft Processor is made, you learn how to verify the design using simulation and an internal logic analyzer. Once complete you will know how to create and use Soft Processors and IP, a very useful skill.
This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or two of video lectures, reading assignments, discussion prompts, and an end of module assessment.
This course will give you hands-on FPGA design experience that uses all the concepts and skills you have developed up to now. You will need to purchase a DE10-Lite development kit. You will setup and test the MAX10 DE10-Lite board using the FPGA design tool Quartus Prime and the System Builder.
Design and test a Binary Coded Decimal Adder.
Design and test a PWM Circuit, with verification by simulation.
Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.
Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file.
Compile your completed hardware using Quartus Prime.
Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.
Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT.
Compile your completed software using the SBT.
Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit.
Record all your observations in a lab notebook pdf.
Submit your project files and lab notebook for grading.
This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.