This course can also be taken for academic credit as ECEA 5360, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Programmable Logic has become more and more common as a core technology used to build electronic systems. By integrating soft-core or hardcore processors, these devices have become complete systems on a chip, steadily displacing general purpose processors and ASICs. In particular, high performance systems are now almost always implemented with FPGAs.
This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. You use FPGA development tools to complete several example designs, including a custom processor. If you are thinking of a career in Electronics Design or an engineer looking at a career change, this is a great course to enhance your career opportunities.
You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. The tools do not run on Apple Mac computers. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, or it may be possible to upgrade the memory.
What's this programmable logic stuff anyway? History and Architecture
What's this programmable logic stuff anyway? In Module 1 you learn about the history and architecture of programmable logic devices including Field Programmable Gate Arrays (FPGAs). You will learn how to describe the difference between an FPGA, a CPLD, an ASSP, and an ASIC, recite the historical development of programmable logic devices; and design logic circuits using LUTs. Examples will include designs of digital adders and multipliers in FPGAs.
FPGA Design Tool Flow; An Example Design
In Module 2 you will install and use sophisticated FPGA design tools to create an example design. You will learn the steps in the standard FPGA design flow, how to use Intel Altera’s Quartus Prime Development Suite to create a pipelined multiplier, and how to verify the integrity of the design using the RTL Viewer and by simulation using ModelSim. Using the TimeQuest timing analyzer, you will analyze the timing of your design to achieve timing closure.
FPGA Architectures: SRAM, FLASH, and Anti-fuse
FPGAs are programmable, and the program resides in a memory which determines how the logic and routing in the device is configured. In Module 3 you will learn the pros and cons of FLASH-based, SRAM-based, and Anti-Fuse based FPGAs. A survey of modern FPGA architectures will give you the tools to determine which type of FPGA is the best fit for a design. Architectures will be explored from the basic core logic cell up to consideration of large Intellectual Property (IP) blocks that are available on many FPGAs.
Programmable logic design using schematic entry design tools
In module 4 you will extend and enhance your design from module 2, completing the design by adding IP blocks, implementing pin assignments and creating a programming file for the FPGA. One outcome will be improved design productivity, by use of design techniques like pipelining, and by the use of system design tools like Qsys, the system design tool in Quartus Prime. You will complete a Qsys system design by creating a NIOS II softcore processor design, which quickly gives you the powerful ability to customize a processor to meet your specific needs.