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University of Colorado Boulder

FPGA Capstone: Building FPGA Projects

University of Colorado Boulder via Coursera

Overview

This course will give you hands-on FPGA design experience that uses all the concepts and skills you have developed up to now. You will need to purchase a DE10-Lite development kit. You will setup and test the MAX10 DE10-Lite board using the FPGA design tool Quartus Prime and the System Builder.
You will:
Design and test a Binary Coded Decimal Adder.
Design and test a PWM Circuit, with verification by simulation.
Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.
Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file.
Compile your completed hardware using Quartus Prime.
Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.
Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT.
Compile your completed software using the SBT.
Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit.
Record all your observations in a lab notebook pdf.
Submit your project files and lab notebook for grading.
This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.

Syllabus

  • Hands on: Altera MAX10 Hardware Setup
    • In this module you will begin your hands-on exploration of FPGA design by setting up a target board, the DE10-Lite based on the MAX10 Intel Altera FPGA. In this module you will
       Setup and test the MAX10 board using the FPGA design tool Quartus Prime and the System Builder.
       Design and test a Binary Coded Decimal Adder Record all your observations in a lab notebook pdf.
       Submit your project files and lab notebook for grading.
      Completing this module will help prepare you for the work to be done in the modules that follow.
  • Develop a Mixed Signal System
    • The goal of this module is to develop a mixed-signal system. You will construct hardware that uses the Analog to Digital Converter (ADC) inputs and Pulse Width Modulate (PWM) outputs to make a voltage measuring instrument. In this module you will
       Create a working design, using most aspects of the Quartus Prime Design Flow.
       Design and test a PWM Circuit, with verification by simulation.
       Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.
       Record all your observations in a lab notebook pdf.
       Submit your project files and lab notebook for grading.
      Completing this module will help prepare you for the work to be done in the modules that follow.
  • Create a System on a Chip with NIOS II
    • The goal of this module is to develop the hardware for a System on a Chip (SoC). You will construct hardware that creates a NIOS II soft processor along with several interfaces to devices on the DE10-Lite development kit. In this module you will
       Create a working design, using most aspects of the Quartus Prime Design Flow.
       Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder). Instantiate this design into a top-level DE10-Lite HDL file.
       Compile your completed hardware using Quartus Prime.
       Record all your observations in a lab notebook.
       Submit your project files and lab notebook for grading.
      Completing this module will provide a platform for the work to be done in the module that follows.
  • Software for a System on a Chip
    • The goal of this module is to develop the software for a System on a Chip (SoC). You will build software for a NIOS II soft processor you built in Module 3, using several interfaces to devices on the DE10-Lite development kit as well. In this module you will
       Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.
       Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder) and the SBT.
       Compile your completed software using the SBT.
       Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit. You will then test your new embedded system.
       Record all your observations in a lab notebook pdf.
       Submit your project files and lab notebook for grading.
      Completing this module will finish your work for this course.

Taught by

Timothy Scherr

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