Design and test a Binary Coded Decimal Adder.
Design and test a PWM Circuit, with verification by simulation.
Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.
Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file.
Compile your completed hardware using Quartus Prime.
Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.
Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT.
Compile your completed software using the SBT.
Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit.
Record all your observations in a lab notebook pdf.
Submit your project files and lab notebook for grading.
This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.