ABOUT THE COURSE: Digital Design is a fundamental course for developing large VLSI designs. This course helps student to understand the internal logic of various combinational units that is needed to develop large VLSI design. The course also introduces the sequential components, clocks and concepts of register transfer level design development process. In this course, we not only introduce the core concepts of digital design, we also introduce hardware description language Verilog. In each module, we will discuss how to implement all fundamental blocks in Verilog. Therefore, this course will help students to understand the internal details of fundamental blocks of digital circuits and also their implementation details.INTENDED AUDIENCE: BTech in CSE, ECE, EIE, MnC second year studentsPREREQUISITES: Basic ElectronicsINDUSTRY SUPPORT: VLSI Industries like Intel, Qualcomm, Samsung, Apple, Xilinx, etc.
Digital Design with Verilog
Indian Institute of Technology Guwahati and NPTEL via Swayam
This course may be unavailable.
Overview
Syllabus
Week 1: Introduction to Digital Design and Switching Algebra
Lecture 1: Introduction to Digital Design
Lecture 2: Switching Algebra
Lecture 3: Number Systems
Week 2: Number Systems and Binary Codes
Lecture 4: Number Systems: Conversion of Bases
Lecture 5: Number Systems: Sign representation,
Lecture 6: 2's complement addition
Lecture 7: Binary Codes
Week 3: Minimization of Switching functions
Lecture 8: Minimization of Boolean functions: Karnaugh Map
Lecture 9: Prime Implicants and Essential Prime Implicants
Lecture 10: Tabulation method
Lecture 11: Prime implicant chart and its reduction, Branching method
Week 4: Multi-level Logic Optimization Heuristic Based Logic
Lecture 12: ESPRESSO: Heuristic-based Logic Optimization
Lecture 13: Prime Implicants and Essential Prime Implicants
Lecture 14: Multi-level Logic Minimization using Prime Implication Chart
Week 5: Introduction to Verilog
Lecture 15: Verilog(Cont)
Lecture 16: Verilog(Cont)
Lecture 17: Verilog
Week 6: Combinational Logic Design: Part 1
Lecture 18: Code Conversion, Parity Checker, Comparator
Lecture 19: Multiplexer, Decoder Decimal Decoder,
Lecture 20: Full-Adder, Ripple Carry Adder
Week 7: Combinational Logic Design: Part 2
Lecture 21: Carry Look ahead adder
Lecture 22: Sign adder, Add/Sub,
Lecture 23: BCD Adder, Multiplier
Lecture 24: Combinational Design using Verilog
Lecture 25: Combinational Design using Verilog
Week 8:
Lecture 26: Sequential Design: Flipflop
Lecture 27: Sequential Design: Counter,
Lecture 28: Sequential Design: Register
Week 9:
Lecture 29: Implementation of FLipflop,
Lecture 30: counters and registers in Verilog
Lecture 31: Finite State Machine Modeling Sequential Design with FSM
Lecture 32: Implementation Methodologies for FSM FSM Minimization
Week 10: Lecture 33: Implementation of FSM using Verilog
Lecture 34: Implementation of FSM using Verilog
Lecture 35:Implementation of FSM using Verilog Lecture 36: Testing of FSM
Week 11:
Lecture 37: Algorithmic State Machine and RTL
Lecture 38: Implementation Methodologies for ASM
Lecture 39: RTL design of Sequential Multiplier using ASM/RTL
Week 12:
Lecture 40: RTL Design using Verilog(Cont)
Lecture 41: RTL Design using Verilog(Cont)
Lecture 42: RTL Design using Verilog
Lecture 1: Introduction to Digital Design
Lecture 2: Switching Algebra
Lecture 3: Number Systems
Week 2: Number Systems and Binary Codes
Lecture 4: Number Systems: Conversion of Bases
Lecture 5: Number Systems: Sign representation,
Lecture 6: 2's complement addition
Lecture 7: Binary Codes
Week 3: Minimization of Switching functions
Lecture 8: Minimization of Boolean functions: Karnaugh Map
Lecture 9: Prime Implicants and Essential Prime Implicants
Lecture 10: Tabulation method
Lecture 11: Prime implicant chart and its reduction, Branching method
Week 4: Multi-level Logic Optimization Heuristic Based Logic
Lecture 12: ESPRESSO: Heuristic-based Logic Optimization
Lecture 13: Prime Implicants and Essential Prime Implicants
Lecture 14: Multi-level Logic Minimization using Prime Implication Chart
Week 5: Introduction to Verilog
Lecture 15: Verilog(Cont)
Lecture 16: Verilog(Cont)
Lecture 17: Verilog
Week 6: Combinational Logic Design: Part 1
Lecture 18: Code Conversion, Parity Checker, Comparator
Lecture 19: Multiplexer, Decoder Decimal Decoder,
Lecture 20: Full-Adder, Ripple Carry Adder
Week 7: Combinational Logic Design: Part 2
Lecture 21: Carry Look ahead adder
Lecture 22: Sign adder, Add/Sub,
Lecture 23: BCD Adder, Multiplier
Lecture 24: Combinational Design using Verilog
Lecture 25: Combinational Design using Verilog
Week 8:
Lecture 26: Sequential Design: Flipflop
Lecture 27: Sequential Design: Counter,
Lecture 28: Sequential Design: Register
Week 9:
Lecture 29: Implementation of FLipflop,
Lecture 30: counters and registers in Verilog
Lecture 31: Finite State Machine Modeling Sequential Design with FSM
Lecture 32: Implementation Methodologies for FSM FSM Minimization
Week 10: Lecture 33: Implementation of FSM using Verilog
Lecture 34: Implementation of FSM using Verilog
Lecture 35:Implementation of FSM using Verilog Lecture 36: Testing of FSM
Week 11:
Lecture 37: Algorithmic State Machine and RTL
Lecture 38: Implementation Methodologies for ASM
Lecture 39: RTL design of Sequential Multiplier using ASM/RTL
Week 12:
Lecture 40: RTL Design using Verilog(Cont)
Lecture 41: RTL Design using Verilog(Cont)
Lecture 42: RTL Design using Verilog
Taught by
Prof. Chandan Karfa, Prof. Aryabartta Sahu
