Overview
The course teaches about architecture-aware, high-performance transactions for persistent memory. The learning outcomes include understanding the challenges of traditional persistent memory transaction systems, learning the design principles of ArchTM, and evaluating its performance against other systems. The course covers skills such as avoiding small writes on persistent memory, encouraging coalescable writes, recovery management, and other optimization techniques. The teaching method involves presenting research findings, system design principles, and performance evaluations. The intended audience for this course includes researchers, developers, and practitioners interested in improving transaction performance on persistent memory.
Syllabus
Intro
Persistent Memory (PM) Has Arrived
PM Architecture & Performance Characterization
Transactions on Persistent Memory
Issues of Existing PM Transactions
Issues of Memory Allocation for PM Transactions
Design Goals of ArchTM
Avoid Small Writes on PM
Encourage Coalescable Writes on PM
Recovery Management
Other Optimization Techniques
Evaluation Setup
Evaluation: TPC-C & TATP
Conclusion
Taught by
USENIX