PLIP- ZedBoard-Zynq AES Peripheral in C - Vivado High Level Synthesis

This course teaches how to implement an AES peripheral in C using Vivado High Level Synthesis (HLS). The learning outcomes include creating a new project, setting up interfaces, exporting to SDK, connecting to the ZedBoard, and running the application. The course focuses on developing skills in Xilinx Platform Studio, AES implementation, driver importing, system initialization, and application execution. The teaching method involves practical demonstrations and hands-on exercises. The intended audience for this course is individuals interested in FPGA development, specifically those working with ZedBoard and Zynq platforms.