The Verilog to Verilog Decompiler

This course aims to teach students how to extract functionality from netlists at a higher abstraction level to reconstruct behavioral Register Transfer Level (RTL) code. The learning outcomes include understanding the terminology of "hardware decompilation," exploring software techniques relevant to hardware decompilation, and learning new techniques unique to hardware decompilation. The course covers topics such as parsing in software and hardware, primitives, flipflops, recompiling in software, basic blocks, graph representation, signature matching, isomorphism-based matching, topology-based matching, subgraph mining, and control flow in software. The teaching method involves a video presentation by an expert in the field. This course is intended for individuals interested in hardware security, firmware, and software development, particularly those looking to recover RTL code from netlists or obsolete parts.